Designing Clock System Using Power Optimization Techniques in Flipflop

-In many digital Very Large Scale Integration design, clock system is one of the most power consumption component. It consumes 30% to 60% of the total system power. As we are in need to reduce the power consumption on portable digital circuit because power budget is severely limited on portable digital circuit. To achieve this requirement, a clock system employing two techniques such as Dual Edge Triggered Sense Amplifier Flip Flop (DETSAFF) and Clock Gated Sense Amplifier Flip Flop (CGSAFF) is proposed. Dual Edge Triggering Sense Amplifier Flip flop will reduce the power consumption up to 30%. Clocked Gated Sense Amplifier Flip Flop (CG SAFF) is engaged when switching activity is less than 0.5. During zero input switching activity, CGSAFF offers up to 86% power saving. We can further reduce the power consumption of the clock system by using low swing differential conditional capturing flip-flop.